The present invention relates to semiconductor storage devices in which gate transistors are connected to memory cells which include capacitors using ferroelectrics. The present invention also relates to methods for driving the semiconductor storage devices.
A conventional semiconductor storage device which includes gain transistors and memory cells having ferroelectric capacitors will be described with reference to accompanying drawings.
FIG. 5 shows the circuit configuration of the conventional ferroelectric memory device.
As shown in FIG. 5, four memory blocks MB00 through MB11 are arranged in the form of a matrix with two rows and two columns. Provided in the memory block MB00, for example, are two memory cells MC00 and MC01, reset transistors QR00 and QRX00, and gain transistors QG00 and QGX00. The memory cell MC00 includes pass transistors QP00 and QPX00 and ferroelectric capacitors C00 and CX00.
The gates of the gain transistors QG00 and QGX00, for example, are connected to sub bit lines SBL00 and SBLX00, respectively, while the respective drains thereof are connected to bit lines BL0 and BLX0 and the respective sources thereof are connected to reset lines RST0 and RSTX0.
The gates of the reset transistors QR00 and QRX00, for example, are connected to a reset transistor control line RE0, while the respective drains thereof are connected to the sub bit lines SBL00 and SBLX00 and the respective sources thereof are connected to the reset lines RST0 and RSTX0.
The bit lines BL0 and BLX0 are connected to a sense amplifier SA0 which includes a cross coupled inverter, for example. The reset lines RST0 and RSTX0 are each connected via a respective switch SW to a ground power source or respective data write circuits WR0 and WRX0.
The memory cell MC00, for example, includes two ferroelectric capacitors C00 and CX00 and two pass transistors QP00 and QPX00. The ferroelectric capacitors C00 and CX00 on the one hand each have an electrode that is connected to a cell plate line CP0. The respective electrodes on the other hand, i.e., storage nodes SN00 and SNX00, of the ferroelectric capacitors C00 and CX00 are connected to the sub bit lines SBL00 and SBLX00 respectively through the pass transistors QP00 and QPX00. The gates of the pass transistors QP00 and QPX00 are connected to a word line WL0. In the two ferroelectric capacitors C00 and CX00 included in the memory cell MC00, data is recorded in a complementary relation in which polarization in the capacitive film in one of the capacitors C00 and CX00 is upward and in the other is downward.
Hereinafter, write and read operations in the conventional semiconductor storage device will be described with reference to timing charts shown in FIGS. 6A and 6B.
(Write Operation)
A case in which data “0” is written into the memory cell MC00 included in the memory block MB00 will be described herein as an example.
First, the switches SW are connected to the ground power source to ground the reset lines RST0 and RSTX0. Thereafter, as shown in FIG. 6A, a high voltage is applied to the word line WL0 and the reset transistor control line RE0 to turn on the pass transistors QP00 and QPX00 and the reset transistors QR00 and QRX00. Subsequently, a positive polarity pulse voltage is applied to the cell plate line CP0, which polarizes the two ferroelectric capacitors C00 and CX00 in the direction (upward as seen in the figure) toward the respective electrodes located close to the storage nodes SN00 and SNX00.
Next, the switches SW are switched to connect the reset line RST0, e.g., with the data write circuit WR0, e.g., so that a positive polarity pulse voltage is applied to the reset line RST0 from the data write circuit WR0. The applied pulse voltage changes the polarization direction in the ferroelectric capacitors C00 to the direction (downward as seen in the figure) toward the electrode thereof located close to the cell plate line CP0. At this time, the other data write circuits WRX0 and WR1, for example, output the ground potential.
It should be noted that when a voltage greater than or equal to the coercive voltage of the ferroelectric is applied across the two electrodes, polarization in the ferroelectric capacitor C00, for example, is directed in the direction of the polarity of the voltage between the electrodes, that is, the direction going from the positive voltage electrode toward the negative voltage electrode.
The write operation as described above makes the polarization directions in the two ferroelectric capacitors C00 and CX00 in the memory cell MC00 different from each other to determine data. The semiconductor storage device including the ferroelectric capacitor C00, for example, keeps its polarization state even if the device is turned off, and thus acts as a non-volatile memory.
(Read Operation)
Referring to the timing chart shown in FIG. 6B, an operation for reading out the data “0” that has been written in the memory cell MC00 in the above-described manner will be described.
In the data read operation, the switches SW are switched for connecting the reset lines RST0 and RSTX0 to the ground power source so that the reset line RST0, for example, is grounded. Further, a pre-charge circuit (not shown) is turned on to pre-charge the bit lines BL0 and BLX0 to a high potential.
Subsequently, as shown in FIG. 6B, a high voltage is applied to the word line WL0 and the reset transistor control line RE0 to turn on the pass transistors QP00 and QPX00 and the reset transistors QR00 and QRX00, so that the storage nodes SN00 and SNX00 of the ferroelectric capacitors C00 and CX00 are reset to a reset potential, that is, the ground potential.
After the storage-node SN00 and SNX00 potentials are reset to the ground potential, the potential of the reset transistor control line RE0 is set low to turn off the reset transistors QR00 and QRX00, and at the same time the pre-charge circuit is turned off. Thereafter, the sense amplifier SA0 is activated, while a positive polarity pulse is applied to the cell plate line CP0. This permits the electric charge to be transferred from the ferroelectric capacitors C00 and CX00 to the gates of the gain transistors QG00 and QGX00, respectively, which causes the respective potentials of the sub bit lines SBL00 and SBLX00 to increase to turn on the gain transistors QG00 and QGX00. As a result, the potentials of the bit lines BL0 and BLX0 drop from their pre-charge level. At this time, since electric charge produced in the downwardly polarized ferroelectric capacitor C00 is greater than electric charge created in the upwardly polarized ferroelectric capacitor CX00, the potential (VSBL00) of the sub bit line SBL00 exceeds the potential (VSBLX00) of the sub bit line SBLX00. As a consequence, the gain transistor QG00 has a channel resistance smaller than that of the gain transistor QGX00, which causes the potential of the bit line BL0 to vary more greatly than the potential of the bit line BLX0. Such difference in the potential variation produces a potential difference between the pair of bit lines BL0 and BLX0, and the resultant potential difference is then multiplied by the sense amplifier SA0.
In the sense amplifier SA0, the stored data is determined as “0” because, of the bit line BL0 and BLX0 pair, the bit line BL0 is of a low potential while the bit line BLX0 is of a high potential. The determination result is then outputted from data output lines DL0 and DLX0 to external devices.
Then, the potential of the reset transistor control line RE0 is set high to turn on the reset transistors such that the storage nodes SN00 and SNX00 are reset to the RST potential, i.e., the ground potential, while the word line WL0 is set to a low potential to turn off the pass transistors QP00 and QPX00, thereby completing the read operation.
The conventional semiconductor storage device, however, has a problem in that a voltage difference (i.e., offset voltage) is produced between the read voltages in the two gain transistors QG00 and QGX00 included in the memory cell MC00, for example, and the offset voltage causes the read margin to decrease.
In the data read operation, the potential difference generated between the complementary sub-bit-line SBL00 and SBLX00 pair, for example, is converted into the channel-resistance difference, and the difference in the drain-source current resulting from the channel-resistance difference is detected by the sense amplifier SA0 as the potential variation created in the bit line BL0 and BLX0 pair.
Since the gain transistors QG00 and QGX00 operate in saturation regions, the drain-source current thereof is proportional to the square of the difference between the gate voltage and the threshold voltage according to a simplified equation for the drain-source current. Given that the respective drain-source currents of the gain transistors QG00 and QGX00 are IDS00 and IDSX00 and that the respective threshold voltage values thereof are VT00 and VTX00, the following equation 1 holds.IDS00/IDSX00=(VSBL00−VT00)2/(VSBLX00−VTX00)2  Equation 1
If it is assumed that the voltages produced in the read operation and the threshold voltages are: VSBL00=1.0 V, VSBLX00=0.9 V, and VT00=VTX00=0.6 V, for example, then IDS00/IDSX00=1.78. Nevertheless, if it is assumed that there is an offset voltage of 0.1 V between the pair of gain transistors QG00 and QGX00, that is, if VT00=0.7 V and VTX00=0.6 V, for example, then IDS00/IDSX00=1. This means that the sense amplifier cannot perform sensing operation.
Such decrease in the drain-source current ratio due to the presence of the offset voltage causes decrease in immunity to noise which enters the sub bit lines when a driving pulse is applied to other wires.
Further, read charge might decrease because of reduced remnant polarization (retention) stored in the ferroelectric capacitors or due to variation (imprint) in the ferroelectric hysteresis caused by elevated-temperature environment. Or a difference in the two ferroelectric capacitors' electric charge caused due to variation created during the manufacturing process, for example, might result in decrease in the potential difference VSBL00—VSBLX00 between the sub bit lines, thereby leading to reduction in the operation margin.
The known methods which have been proposed to deal with the above problems include a method for canceling offset voltage in a sense amplifier by accumulating the offset voltage in a capacitor (disclosed in Japanese Laid-Open Publication No. 07-302497), a method for reducing offset voltage by providing the sense amplifier with trimming function (disclosed in Japanese Laid-Open Publication No. 10-162585), and a method for compensating for offset voltage by adjusting the well potential of MOS transistors forming the sense amplifier (disclosed in Japanese Laid-Open Publication No. 2000-311491).
However, the methods disclosed in those publications are to cancel offset voltage created in a sense amplifier and not to cancel offset voltage produced in a gain transistor which is connected to a memory cell.